Quarter-rate clock recovery circuit and clock recovering method using the same

Abstract

A quarter-rate clock recovery circuit includes a clock generator, a phase interpolation unit, a phase detector, and a controller. The clock generator generates first through fourth clocks having a quarter frequency of a data-rate of input data, the second, third and fourth clocks have phase differences of 90, 180, and 270 degrees with respect to a phase of the first clock, respectively. The phase interpolation unit performs a phase interpolation on the first through fourth clocks based on control signals to generate fifth through eighth clocks that have a quarter frequency of the data-rate of the input data, the fifth clock tracking a phase of the input data, the sixth, seventh, and eighth clocks respectively have phase differences of 45, 90, and 135 degree with respect to a phase of the fifth clock. The phase detector outputs signals corresponding to phase differences between the input data and the fifth through eighth clocks based on the input data and the fifth through eighth clocks. The controller generates the control signals to control the phase interpolation unit based on the signals output from the phase detector.