Floating-gate non-volatile memory architecture for improved negative bias distribution

Abstract

A floating-gate non-volatile memory is composed of a plurality of banks, and a negative bias power line providing a negative bias for the plurality of banks. Each of the plurality of banks includes a plurality of sectors arranged in columns, each comprising a plurality of floating-gate memory cells; a plurality of column decoders associated with the columns of the sectors, respectively; and a bank decoder connected to the plurality of column decoders through an in-bank power line. A bank decoder within selected one of the banks provides the negative bias received from the negative bias power line for the in-bank power line. Each of the column decoders is responsive to selection/non-selection of associated one of the columns of the sectors for generating a negative voltage signal from the negative bias received from the in-bank power line, and providing the negative voltage signal for the associated one of the columns of the sectors.