The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2009

Filed:

Mar. 03, 2006
Applicants:

Teunis Jan Ikkink, Geldrop, NL;

Pierre Hermanus Woerlee, Valkenswaard, NL;

Victor Martinus Van Acht, Waalre, NL;

Nicolaas Lambert, Waalre, NL;

Albert W. Marsman, Valkenswaard, NL;

Inventors:

Teunis Jan Ikkink, Geldrop, NL;

Pierre Hermanus Woerlee, Valkenswaard, NL;

Victor Martinus Van Acht, Waalre, NL;

Nicolaas Lambert, Waalre, NL;

Albert W. Marsman, Valkenswaard, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A control circuit () for a memory matrix is used that defines a write process that uses circuit state transitions between at least two idle circuit states, an all column update circuit state and a column selective update state. In the second. During access the control circuit switches back and forth to the column selective update state (W) from the first idle state (II) during execution of a column selective update command and back and forth to the all-column update state (E) from the second idle state () during execution of an all column update command. The control circuit () is retained in the first and second idle state (II,), without switching to the second and first idle state (, II) between execution of successive column selective update commands and all column update commands respectively.


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