The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 25, 2009
Filed:
Oct. 21, 2005
Timothy Davis, Arlington, TX (US);
Timothy Davis, Arlington, TX (US);
Via Technologies, Inc., Hsin-Tien, Taipei, TW;
Abstract
Circuits and methods for protecting a circuit from an electrostatic discharge (ESD) event are disclosed herein. One such method includes detecting when a circuit to be protected is powering up and disabling an output driver of the circuit to be protected when the circuit is powering up. The power up sequence, for example, may be the result of a sensed ESD event. In addition, the present disclosure includes a circuit that comprises an ESD sensing circuit and a disable circuit. The ESD sensing circuit includes an RC circuit connected between VDD and VSS and a first inverter connected between a second inverter and a node that connects a resistor with a capacitor of the RC circuit. The disable circuit includes a first PMOS transistor and a first NMOS transistor, the first PMOS transistor configured to receive an EN signal from the second inverter, and the first NMOS transistor configured to receive ansignal from the first inverter. The first PMOS transistor is further configured to connect a second PMOS transistor to VDD when EN is low, and the first NMOS transistor is further configured to connect a second NMOS transistor to VSS whenis high.