The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 25, 2009
Filed:
Jun. 30, 2006
Michael D. Hutton, Mountain View, CA (US);
David Cashman, Toronto, CA;
Jinyoung Yuan, Cupertino, CA (US);
Kimberly Anne Bozman, Toronto, CA;
Michael D. Hutton, Mountain View, CA (US);
David Cashman, Toronto, CA;
Jinyoung Yuan, Cupertino, CA (US);
Kimberly Anne Bozman, Toronto, CA;
Altera Corporation, San Jose, CA (US);
Abstract
A programmable logic device architecture providing efficient configurable functionality to allow the 'tie-off' of logic region-wide control signals. This functionality is provided while maintaining the efficiency of region-wide signals, yet allows sufficient flexibility for effective use of register-packing and usage within the region. Methods are given for both sub-region and individual logic element tie-off granularity. In various embodiments, the tie-off logic may be used for logic wide signals used in PLDs having logic elements arranged in regions of logic, sometimes referred to in the industry as either Logic Array Blocks or Complex Logic Blocks.