The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2009

Filed:

Apr. 08, 2004
Applicants:

Benjamin N. Eldridge, Danville, CA (US);

Igor Y. Khandros, Orinda, CA (US);

Gaetan L. Mathieu, Livermore, CA (US);

David V. Pedersen, Scotts Valley, CA (US);

Inventors:

Benjamin N. Eldridge, Danville, CA (US);

Igor Y. Khandros, Orinda, CA (US);

Gaetan L. Mathieu, Livermore, CA (US);

David V. Pedersen, Scotts Valley, CA (US);

Assignee:

FormFactor, Inc., Livermore, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Spring contact elements are fabricated by depositing at least one layer of metallic material into openings defined in masking layers deposited on a surface of a substrate which may be an electronic component such as an active semiconductor device. Each spring contact element has a base end, a contact end, and a central body portion. The contact end is offset in the z-axis (at a different height) and in at least one of the x and y directions from the base end. In this manner, a plurality of spring contact elements are fabricated in a prescribed spatial relationship with one another on the substrate. The spring contact elements make temporary (i.e., pressure) or permanent (e.g., joined by soldering or brazing or with a conductive adhesive) connections with terminals of another electronic component to effect electrical connections therebetween. In an exemplary application, the spring contact elements are disposed on a semiconductor devices resident on a semiconductor wafer so that temporary connections can be made with the semiconductor devices to burn-in and/or test the semiconductor devices.


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