The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2009

Filed:

Jan. 16, 2007
Applicants:

Sang-kyoung Lee, Incheon-Gwangyeoksi, KR;

Jin-hong Kim, Suwon-si, KR;

Dong-hwan Kim, Suwon-si, KR;

Won-sik Shin, Seoul, KR;

Woong Lee, Seoul, KR;

Inventors:

Sang-Kyoung Lee, Incheon-Gwangyeoksi, KR;

Jin-Hong Kim, Suwon-si, KR;

Dong-Hwan Kim, Suwon-si, KR;

Won-Sik Shin, Seoul, KR;

Woong Lee, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a nonvolatile memory device includes forming a plurality of device isolation regions in a semiconductor substrate, forming a tunneling insulation layer on the semiconductor substrate, forming a first preliminary polysilicon layer in communication with the tunneling insulation layer and the device isolation regions, forming a preliminary amorphous silicon layer on the first preliminary silicon layer, forming a second preliminary polysilicon layer on the preliminary amorphous silicon layer, and patterning the second preliminary polysilicon layer, the preliminary amorphous silicon layer, and the first preliminary polysilicon layer to form a floating gate layer.


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