The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 25, 2009
Filed:
Mar. 30, 2007
Thomas J. Swirbel, Davie, FL (US);
Thomas J. Swirbel, Davie, FL (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A method for fabricating a low cost integrated circuit package () includes separating a processed silicon wafer into a plurality of individual die () and then positioning the die () on a secondary substrate in a face down position for allowing an increased die I/O connection area. The die is covered () with one or more epoxy materials to form a group of embedded die packages. One or more pads on the die are then exposed () and subsequently connected () to an I/O connection in a die I/O connection area. Each of the die are then separated () forming singular embedded die packages from the secondary substrate. The method provides a manufacturing process to form a low cost, very high density integrated circuit package using a combination of both wafer scale packaging and wafer level packaging processes.