The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7577884 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 18, 2009

Filed:

Jun. 06, 2003
Applicants:

Kiyonori Ogura, Kasugai, JP;

Yasunori Murase, Kasugai, JP;

Inventors:

Kiyonori Ogura, Kasugai, JP;

Yasunori Murase, Kasugai, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device that performs refresh tests of a plurality of individual memories built into the same chip and prevents excessive testing during the refresh test. When a first testing circuit enters a wait state, the first testing circuit issues a refresh command REF to a first memory circuit. Then, the first memory circuit refreshes the memory cells until a second testing circuit enters the wait state. That is, since the memory cells of the first memory circuit are refreshed until the writing to a second memory circuit ends, the refresh test time of the first and second memory circuits are the same.


Find Patent Forward Citations

Ogura, Kiyonori. (2009). Memory circuit testing system, semiconductor device, and memory testing method (U.S. Patent No. 7577884). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7577884

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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