Simulator and simulation method for behaviors of processors

Abstract

A simulator operable to simulate behaviors of a processor using software is provided. The simulator includes a command input unit, a memory element, a register element, a control element, a resource information storage unit, and a resource access-analyzing unit. The command input unit is operable to analyze/process entered commands. The memory element is operable to store executive instructions issued by the processor and data treated by the processor. The register element is operable to contain data for use in calculation. The control element is operable to access the memory element and register element in accordance with the executive instructions. The resource information storage unit is operable to contain specified resource information and a piece of read/write information for each piece of the resource information. The resource access-analyzing unit is operable to compare access destinations (the memory element and register element to be accessed by the control element) and a read/write classification with the resource information and read/write information contained in the resource information storage unit, thereby practicing a resource access analysis as to whether or not the access destinations are allowed by the resource information and read/write information.