The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 18, 2009
Filed:
Jul. 18, 2005
Eizo Fukui, Tokyo, JP;
Kouzou Ichimaru, Oita, JP;
Eizo Fukui, Tokyo, JP;
Kouzou Ichimaru, Oita, JP;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
The objective of the present invention is to present a buffer circuit by which a load can be driven at a high speed while restraining an increase in power consumption. A current input to npn transistor Qvia node Nis detected by current detection circuitAt bias control circuitbase voltage of npn transistor Qis regulated in such a manner that the current of npn transistor Qdecreases in accordance with an increase in said detected current, and the current of npn transistor Qincreases in accordance with a decrease in the detected current. As a result, because transient current which can flow to the load can be increased, even when load capacitor CL has a large capacitance or when the frequency is high, the output voltage can quickly follow a change in the input voltage, so that distortion of the output voltage waveform can be restrained.