The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 18, 2009
Filed:
Nov. 27, 2007
Dae Woo Lee, Daejeon, KR;
Yil Suk Yang, Daejeon, KR;
Ik Jae Chun, Daejeon, KR;
Chun Gi Lyuh, Daejeon, KR;
Tae Moon Roh, Daejeon, KR;
Jong Dae Kim, Daejeon, KR;
Dae Woo Lee, Daejeon, KR;
Yil Suk Yang, Daejeon, KR;
Ik Jae Chun, Daejeon, KR;
Chun Gi Lyuh, Daejeon, KR;
Tae Moon Roh, Daejeon, KR;
Jong Dae Kim, Daejeon, KR;
Electronics and Telecommunications Research Institute, Daejeon, KR;
Abstract
Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage current in the clock gating circuit is reduced in a sleep mode, and supply of a clock to a unused device of a targeted logic circuit is prevented by the control of a clock enable signal in an active mode, thereby reducing power consumption. The low-power clock gating circuit using an MTCMOS technique uses devices having a low threshold voltage and devices having a high threshold voltage, which makes it possible to implement a high-speed, low-power circuit, unlike a conventional clock gating circuit using a single threshold voltage.