The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 18, 2009
Filed:
Nov. 14, 2006
Seong-chan Han, Cheonan-si, KR;
Dong-chun Lee, Cheonan-si, KR;
Kwang-su Yu, Cheonan-si, KR;
Dong-woo Shin, Cheonan-si, KR;
Hyo-jae Bang, Cheonan-si, KR;
Hyun-seok Choi, Cheonan-si, KR;
Si-suk Kim, Cheonan-si, KR;
Seong-Chan Han, Cheonan-si, KR;
Dong-Chun Lee, Cheonan-si, KR;
Kwang-Su Yu, Cheonan-si, KR;
Dong-Woo Shin, Cheonan-si, KR;
Hyo-Jae Bang, Cheonan-si, KR;
Hyun-Seok Choi, Cheonan-si, KR;
Si-Suk Kim, Cheonan-si, KR;
Samsung Electronic Co., Ltd., Gyeonggi-do, KR;
Abstract
Example embodiments may be directed to a printed circuit board having an insulating substrate, pads disposed on the surface of the insulating substrate, a solder resist, and a solder moving portion. Leads of a semiconductor package may be mounted on the insulating substrate. The pads to which the leads of the semiconductor package are connected may be disposed on the surface of the insulating substrate. The solder resist layer may cover the insulating substrate, but may also contain openings exposing at least a portion of the pads to which the leads of the semiconductor package are connected. During the process by which each semiconductor lead is connected to a pad, the solder moving portion on the pad may allow an adhesion solder coating each of the leads of the semiconductor package to move towards a shoulder portion of the semiconductor package leads.