The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2009

Filed:

Feb. 28, 2006
Applicants:

Ruben P. Madrid, Lapu-lapu, PH;

Romel N. Manatad, Mandaue, PH;

Inventors:

Ruben P. Madrid, Lapu-lapu, PH;

Romel N. Manatad, Mandaue, PH;

Assignee:

Fairchild Semiconductor Corporation, South Portland, ME (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention claimed is a packaged semiconductor device with dual exposed surfaces and a method of manufacturing the device. A thermal clip and one or multiple source pads are exposed on opposite ends of the device through a nonconductive molding material used to package the device. The thermal clip and source pad can be either top or bottom-exposed. The gate, source and drain leads are exposed through the molding material, and all leads are coplanar with the bottom-exposed surface. The device can have multiple semiconductor dies or various sized dies while still having a single, constant footprint. The method of manufacturing requires attaching the semiconductor die to a thermal clip, and then attaching the die with the attached thermal clip to a lead frame. The resulting device is then molded, marked, trimmed and singulated, in this order, creating a packaged semiconductor device with dual exposed surfaces.


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