The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2009

Filed:

Aug. 08, 2007
Applicants:

Christopher Sean Olsen, Fremont, CA (US);

Sunderraj Thirupapuliyur, Sunnyvale, CA (US);

Inventors:

Christopher Sean Olsen, Fremont, CA (US);

Sunderraj Thirupapuliyur, Sunnyvale, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

Defects and fixed charge in a gate dielectric near the gate dielectric-substrate interface are reduced by performing a gate dielectric relaxation anneal step prior to source-drain ion implantation, in which the wafer temperature is ramped gradually to near a melting temperature of the substrate equal to a peak post-ion implantation anneal peak temperature. The ramping rates are sufficiently gradual so that the gate dielectric is held above its reflow temperature for a significant duration.


Find Patent Forward Citations

Olsen, Christopher. (2009). Gate interface relaxation anneal method for wafer processing with post-implant dynamic surface annealing (U.S. Patent No. 7575986). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7575986

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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