The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7575967 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 18, 2009

Filed:

Oct. 18, 2006
Applicants:

Naoto Saitoh, Chiba, JP;

Yuichiro Kitajima, Chiba, JP;

Inventors:

Naoto Saitoh, Chiba, JP;

Yuichiro Kitajima, Chiba, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/72 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a manufacturing method for a semiconductor device, a first impurity diffusion layer for a low impurity concentration drain of a second conductivity type is formed within a semiconductor layer of a first conductivity type, and a second impurity diffusion layer for a high impurity concentration drain of the second conductivity type is formed adjacent to the first impurity diffusion layer, with the second impurity diffusion layer having a higher impurity concentration than the first impurity diffusion layer. An interlayer insulating film is formed on the semiconductor substrate layer. A drain extension region having a high thermal conductivity is formed on a surface of the first impurity diffusion layer. A contact hole is formed through the interlayer insulating film and up to the second impurity diffusion layer. A wiring metal layer is then deposited into the contact hole to form therein a drain electrode that is electrically connected to the second impurity diffusion layer and that is disposed apart from and not in contact with the drain extension region.


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