The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2009

Filed:

Jun. 09, 2006
Applicants:

Jeffrey C. Ward, Thornton, CO (US);

James Ogden, San Jose, CA (US);

Mark R. Mclaughlin, El Sobrante, CA (US);

Jerome Bertrand, Grenoble, FR;

Michael G. Ingoldby, Boulder, CO (US);

Inventors:

Jeffrey C. Ward, Thornton, CO (US);

James Ogden, San Jose, CA (US);

Mark R. McLaughlin, El Sobrante, CA (US);

Jerome Bertrand, Grenoble, FR;

Michael G. Ingoldby, Boulder, CO (US);

Assignee:

XILINX, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of integrating a High-level Language (HLL) function with a Hardware Description Language (HDL) representation of a circuit design can include identifying an attribute of the HDL representation of the circuit design that is resolved at compile time and determining a value for the attribute using an HLL function when compiling the HDL representation of the circuit design.


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