The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2009

Filed:

Jan. 29, 2007
Applicants:

Chidamber R. Kulkarni, Santa Clara, CA (US);

Gordon J. Brebner, Los Gatos, CA (US);

Eric R. Keller, Boulder, CO (US);

Philip B. James-roxby, Longmont, CO (US);

Inventors:

Chidamber R. Kulkarni, Santa Clara, CA (US);

Gordon J. Brebner, Los Gatos, CA (US);

Eric R. Keller, Boulder, CO (US);

Philip B. James-Roxby, Longmont, CO (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, specification data is received that includes attributes of the memory system. A logical description of the memory system is generated in response to the specification data. The logical description defines a memory component and a memory-interconnection component. A physical description of the memory system is generated in response to the logical description. The physical description includes memory circuitry associated with the integrated circuit defined by the memory component. The memory circuitry includes an interconnection topology defined by the memory interconnection component.


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