The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2009

Filed:

Sep. 21, 2005
Applicants:

Satoru Shimoda, Fussa, JP;

Tomoyuki Shirasaki, Higashiyamato, JP;

Jun Ogura, Fussa, JP;

Minoru Kumagai, Tokyo, JP;

Inventors:

Satoru Shimoda, Fussa, JP;

Tomoyuki Shirasaki, Higashiyamato, JP;

Jun Ogura, Fussa, JP;

Minoru Kumagai, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
Abstract

A transistor array substrate includes a plurality of driving transistors which are arrayed in a matrix on a substrate. The driving transistor has a gate, a source, a drain, and a gate insulating film inserted between the gate, and the source and drain. A plurality of signal lines are patterned together with the gates of the driving transistors and arrayed to run in a predetermined direction on the substrate. A plurality of supply lines are patterned together with the sources and drains of the driving transistors and arrayed to cross the signal lines via the gate insulating film. The supply line is electrically connected to one of the source and the drain of the driving transistor. A plurality of feed interconnections are formed on the supply lines along the supply lines, respectively.


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