The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 2009
Filed:
Oct. 26, 2004
Laurence D. Lewicki, Sunnyvale, CA (US);
Amjad T. Obeidat, Santa Clara, CA (US);
Nicolas Nodenot, Mountain View, CA (US);
Laurence D. Lewicki, Sunnyvale, CA (US);
Amjad T. Obeidat, Santa Clara, CA (US);
Nicolas Nodenot, Mountain View, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A system and method is disclosed for providing a clock and data recovery circuit with a fast bit error rate self test capability. A bit error rate test control unit is provided that causes the clock and data recovery circuit to sample data adjacent to an edge of a bit period to create errors at a relatively high bit error rate. This is accomplished by intentionally introducing an interpolator offset in a phase position of a data clock signal. The test control unit generates a first bit error rate and then subsequently generates a second bit error rate. The test control unit then uses the values of the first and second bit error rates to extrapolate a value of bit error rate for the clock and data recovery circuit that corresponds to a zero value of interpolator offset.