The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2009

Filed:

May. 01, 2008
Applicants:

Scott B. Frommer, Cold Spring, NY (US);

Sheldon B. Levenstein, Austin, TX (US);

Bruce J. Ronchetti, Austin, TX (US);

Anthony Saporito, Hyde Park, NY (US);

Inventors:

Scott B. Frommer, Cold Spring, NY (US);

Sheldon B. Levenstein, Austin, TX (US);

Bruce J. Ronchetti, Austin, TX (US);

Anthony Saporito, Hyde Park, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.


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