The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2009
Filed:
Jul. 09, 2004
Hiroshi Tanaka, Tokyo, JP;
Yohei Akita, Tokyo, JP;
Tetsuro Honmura, Sagamihara, JP;
Fumio Arakawa, Tokyo, JP;
Takanobu Tsunoda, Tokyo, JP;
Hiroshi Tanaka, Tokyo, JP;
Yohei Akita, Tokyo, JP;
Tetsuro Honmura, Sagamihara, JP;
Fumio Arakawa, Tokyo, JP;
Takanobu Tsunoda, Tokyo, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in configuration information. The circuit has an input switch ISW connected to multiple data input nodes, an output switch OSW connected to multiple data output nodes, a first data path containing an arithmetic logic circuit ALU and a result storage flip-flop CFFbetween the input switch ISW and output switch OSW. The second data path containing a data transfer flip-flop between an input switch ISW and an output switch OSW, and the result storage flip-flop CFF stores the calculated result data from the arithmetic logic circuit ALU, and the data transfer flip-flop holds data input from any of the multiple data input nodes.