The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7567587 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 28, 2009

Filed:

Jan. 09, 2004
Applicants:

Kevin Mlazgar, Vancouver, CA;

Pierre Vaillancourt, Vancouver, CA;

Alexandre Fortin, Laval, CA;

Inventors:

Kevin Mlazgar, Vancouver, CA;

Pierre Vaillancourt, Vancouver, CA;

Alexandre Fortin, Laval, CA;

Assignee:

PMC-Sierra, Inc., Santa Clara, unknown;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04J 3/24 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and architecture for the extraction of data from or the insertion of data into Synchronous Optical Network (SONET) or Synchronous Digital Hierarchy (SDH) frames is disclosed. The method and architecture provides an interface that permits the time-multiplexed data streams being extracted or inserted to have variable data-rates and no fixed alignment with respect to each other. The extraction and insertion interface accommodates for variable POH data rates and alignment inconsistencies of POH bytes amongst different paths due to floating pointer positions. The interface operates at the lowest possible frequency that can still accommodate the minimum spacing between any two consecutive words of data for a given data stream. In the insertion case, the frequency of operation chosen also allows the pipelining of requests as well as the pipelining of the subsequent associated data in response. The implementation of the present invention minimizes the amount of storage and enables a relatively low required frequency of operation while maintaining a smooth clock. In addition, in the insertion case, the pipelined nature of the interface provides flexibility in meeting interface timing.


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