The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2009
Filed:
Oct. 30, 2007
Hagop Nazarian, San Jose, CA (US);
Harry Kuo, Cupertino, CA (US);
Michael Achter, Mountain View, CA (US);
Hagop Nazarian, San Jose, CA (US);
Harry Kuo, Cupertino, CA (US);
Michael Achter, Mountain View, CA (US);
Spansion LLC, Sunnyvale, CA (US);
Abstract
An apparatus comprising a two or three dimensional array of a plurality of pairs of non-volatile memory ('NVM') cells coupled to enable program and erase of the NVM cells. The plurality of pairs of NVM cells is electrically connected to word lines and bit lines. Each pair of NVM cells comprises a first memory cell and a second memory cell. The first and second memory cells comprise a first source/drain, a second source/drain, and a control gate. The first source/drain of the first memory cell is connected to one of the bit lines. The second source/drain of the first memory cell is connected to the first source/drain of the second memory cell. The second source/drain of the second memory cell is connected to another one of the bit lines. The control gates of the first and second memory cells are connected to different word lines.