The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2009

Filed:

Dec. 17, 2007
Applicants:

Min-wook Park, Yongin-si, KR;

Bum-ki Baek, Suwon-si, KR;

Jeong-young Lee, Yongin-si, KR;

Kwon-young Choi, Goyang-si, KR;

Sang-ki Kwak, Suwon-si, KR;

San-jin Jeon, Seoul, KR;

Inventors:

Min-Wook Park, Yongin-si, KR;

Bum-Ki Baek, Suwon-si, KR;

Jeong-Young Lee, Yongin-si, KR;

Kwon-Young Choi, Goyang-si, KR;

Sang-Ki Kwak, Suwon-si, KR;

San-Jin Jeon, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A thin film transistor array panel is provided, which includes a substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a plurality of ohmic contacts formed on the semiconductor layer; source and drain electrodes formed on the ohmic contacts; a passivation layer formed on the source and the drain electrodes and having a first contact hole exposing a portion of the drain electrode and an opening exposing a first portion of the semiconductor layer and having edges that coincide with edges of the source and the drain electrodes; and a pixel electrode formed on the passivation layer and contacting the drain electrode through the first contact hole.


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