The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2009
Filed:
Jul. 11, 2006
Wenxu Xianyu, Suwon-si, KR;
Young-soo Park, Suwon-si, KR;
Takashi Noguchi, Yongin-si, KR;
Hans S. Cho, Seoul, KR;
Xiaoxin Zhang, Yongin-si, KR;
Huaxiang Yin, Yongin-si, KR;
Wenxu Xianyu, Suwon-si, KR;
Young-Soo Park, Suwon-si, KR;
Takashi Noguchi, Yongin-si, KR;
Hans S. Cho, Seoul, KR;
Xiaoxin Zhang, Yongin-si, KR;
Huaxiang Yin, Yongin-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
Provided may be a method of fabricating nanowires and a method of fabricating a transistor having the same. The method may include: forming a template layer on a substrate, the template layer having a first lateral surface and a second lateral surface facing the first surface; forming pores in the template layer, the pores disposed between the first lateral surface and the second lateral surface in the template layer and having first apertures in the first lateral surface; forming a single-crystalline material layer contacting the first apertures disposed in the first lateral surface of the template layer; forming second apertures connecting pores disposed in the second lateral surface; supplying gaseous crystal growth materials through the second apertures; and forming crystalline nanowires in the pores by crystal growth from the single-crystalline material layer. The nanowires may be made of crystalline materials, e.g., Si or SiGe, and may be formed parallel to the substrate. Higher quality nanowires, whose orientation may be controlled, may be formed. A higher quality transistor may be formed on the substrate by applying a method of fabricating the nanowires.