The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 2009
Filed:
Nov. 21, 2003
Gregg Baeckler, San Jose, CA (US);
Martin Langhammer, Salisbury, GB;
James Schleicher, Santa Clara, CA (US);
Richard Yuan, Cupertino, CA (US);
Gregg Baeckler, San Jose, CA (US);
Martin Langhammer, Salisbury, GB;
James Schleicher, Santa Clara, CA (US);
Richard Yuan, Cupertino, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Logic circuits that support the addition of three binary numbers using hardwired adders are described. In one embodiment, this is accomplished by using a 3:2 compressor (i.e., a Carry Save Adder method), using hardwired adders to add the sums and carrys produced by the 3:2 compression, and sharing carrys data calculated in one logic element ('LE') with the following LE. In such an embodiment, with the exception of the first and last LEs in a logic array block ('LAB'), each LE in effect lends one look-up table (“LUT”) to the LE below (i.e., the following LE) and borrows one LUT from the LE above (i.e., the previous LE). The LUT being lent or borrowed is one that implements the carry function in the 3:2 compressor model. In another aspect, an embodiment of the present invention provides LEs that include selectors to select signals corresponding to the addition of three binary numbers mode.