The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 2009
Filed:
Dec. 08, 2006
Hyun-won Mun, Yongin-si, KR;
Il-ku Nam, Anyang-si, KR;
Sang-yeob Lee, Suwon-si, KR;
Min-kyu Je, Anyang-si, KR;
Hyun-Won Mun, Yongin-si, KR;
Il-Ku Nam, Anyang-si, KR;
Sang-Yeob Lee, Suwon-si, KR;
Min-Kyu Je, Anyang-si, KR;
Samsung Electronics Co., Ltd., Suwon-Si, KR;
Abstract
A voltage reference circuit and a current reference circuit using a vertical bipolar junction transistor (BJT) implemented by a deep N-well complementary metal-oxide semiconductor (CMOS) process, wherein the voltage reference circuit generates a constant reference voltage regardless of temperature and includes an amplifier element having a positive input terminal and a negative input terminal, a first transistor, and a second transistor. The first transistor is electrically connected to the positive input terminal and the second transistor is electrically connected to the negative input terminal. Each of the first and second transistors is a vertical BJT implemented by a deep N-well CMOS process, and the reference voltage is calculated by adding a base-emitter voltage of one of the first and second transistors to a value obtained by multiplying a thermal voltage by a predetermined factor. Accordingly, circuits having better reproducibility, uniformity, and device matching than circuits that use a lateral NPN/PNP device or substrate NPN/PNP device manufactured using a CMOS process are provided.