The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2009

Filed:

May. 14, 2007
Applicants:

Shawn K. Morrison, San Jose, CA (US);

James J. Koning, Mountain View, CA (US);

Greg W. Starr, San Jose, CA (US);

John D. Logue, Placerville, CA (US);

Robert M. Ondris, Santa Clara, CA (US);

Inventors:

Shawn K. Morrison, San Jose, CA (US);

James J. Koning, Mountain View, CA (US);

Greg W. Starr, San Jose, CA (US);

John D. Logue, Placerville, CA (US);

Robert M. Ondris, Santa Clara, CA (US);

Assignee:

XILINX, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/094 (2006.01);
U.S. Cl.
CPC ...
Abstract

Preventing transistor damage to an integrated circuit is described. The circuit includes a switch with a first pair of p-type transistors respectively coupled in source-drain parallel with second pair of p-type transistors for preventing Negative Bias Temperature Instability ('NBTI') damage to the second pair of p-type transistors. The switch is configured to such that when in a state associated with causing, or potentially causing, NBTI damage, both of the second pair of p-type transistors are in an OFF state for preventing NBTI damage thereto.


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