The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2009

Filed:

Apr. 20, 2006
Applicants:

James T. Walker, Palo Alto, CA (US);

Jimes Lei, Milpitas, CA (US);

Inventors:

James T. Walker, Palo Alto, CA (US);

Jimes Lei, Milpitas, CA (US);

Assignee:

Supertex, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/0175 (2006.01);
U.S. Cl.
CPC ...
Abstract

A high speed logic signal level shifter is comprised of: a logic signal buffer for receiving logic signal information and having true and complement state differential outputs; a binary flip-flop circuit with set and reset inputs; a first coupling capacitor connected from the true buffer output to the set input of the binary flip-flop circuit; and a second coupling capacitor connected from the complement buffer output to the reset input of the binary flip-flop circuit. The high speed logic signal level shifter transfers a fast logic signal across a high voltage difference by making use of rapid voltage changes transmitted through small capacitors. The signal changes carried by the capacitors are about 10 times faster than any expected voltage transient on VPP or VNN. Furthermore, the differential coupling circuit is used to provide enhanced protection against undesired circuit switching during supply voltage changes.


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