The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 2009
Filed:
Dec. 06, 2004
Jang-yeon Kwon, Seoul, KR;
Min-koo Han, Seoul, KR;
Se-young Cho, Seoul, KR;
Kyung-bae Park, Seoul, KR;
Do-young Kim, Gyeonggi-do, KR;
Min-cheol Lee, Seoul, KR;
Sang-myeon Han, Seoul, KR;
Takashi Noguchi, Gyeonggi-do, KR;
Young-soo Park, Gyeonggi-do, KR;
Ji-sim Jung, Incheon-si, KR;
Jang-yeon Kwon, Seoul, KR;
Min-koo Han, Seoul, KR;
Se-young Cho, Seoul, KR;
Kyung-bae Park, Seoul, KR;
Do-young Kim, Gyeonggi-do, KR;
Min-cheol Lee, Seoul, KR;
Sang-myeon Han, Seoul, KR;
Takashi Noguchi, Gyeonggi-do, KR;
Young-soo Park, Gyeonggi-do, KR;
Ji-sim Jung, Incheon-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
A method of fabricating a poly-Si thin film and a method of fabricating a poly-Si TFT using the same are provided. The poly-Si thin film is formed at a low temperature using inductively coupled plasma chemical vapor deposition (ICP-CVD). After the ICP-CVD, excimer laser annealing (ELA) is performed while increasing energy by predetermined steps. A poly-Si active layer and a SiOgate insulating layer are deposited at a temperature of about 150° C. using ICP-CVD. The poly-Si has a large grain size of about 3000 Å or more. An interface trap density of the SiOcan be as high as 10/cm. A transistor having good electrical characteristics can be fabricated at a low temperature and thus can be formed on a heat tolerant plastic substrate.