The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 2009
Filed:
Mar. 27, 2007
Choon Keun Lee, Gyunggi-do, KR;
Seung Hyun Ra, Gyunggi-do, KR;
Sang Moon Lee, Seoul, KR;
Jung Woo Lee, Gyunggi-do, KR;
Jeong Bok Kwak, Gyunggi-do, KR;
Jae Choon Cho, Gyunggi-do, KR;
Chi Seong Kim, Gyunggi-do, KR;
Choon Keun Lee, Gyunggi-do, KR;
Seung Hyun Ra, Gyunggi-do, KR;
Sang Moon Lee, Seoul, KR;
Jung Woo Lee, Gyunggi-do, KR;
Jeong Bok Kwak, Gyunggi-do, KR;
Jae Choon Cho, Gyunggi-do, KR;
Chi Seong Kim, Gyunggi-do, KR;
Samsung Electro-Mechanics Co., Ltd., Suwon, KR;
Abstract
Disclosed is a method of manufacturing a printed circuit board for fine circuit formation, in which an unnecessary metal layer formed on the upper portion of a circuit pattern is removed through mechanical polishing and then chemical etching. In place of expensive chemical mechanical polishing, in the method of the invention, mechanical polishing and chemical etching are continuously applied to thus sequentially remove and planarize the unnecessary metal layer. Thereby, through an inexpensive, simple, and continuous process, the planarization procedure can be precisely performed, thus making it possible to apply the method to large areas and economically realize a fine circuit pattern.