Method and device for verifying timing in a semiconductor integrated circuit

Abstract

A timing verification device for performing effective timing verification while correctly taking variation into account. The timing verification device receives a technology file and extracts a coefficient of variation for each cell based on conditions of the manufacturing process of a semiconductor integrated circuit. The timing verification device receives a timing list and computes the variation amounts corresponding to the rise and fall of a clock signal or a correction coefficient obtained by taking into account the correlation between the rise and the fall based on the extracted coefficients of variation. The timing verification device re-computes a delay time using the amount of variation or the correction coefficient and determines the pulse width and the timing based on the recomputed delay time to output the determination result as a timing report.