The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7562265 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 14, 2009

Filed:

Mar. 23, 2004
Applicants:

Michael J. Azevedo, San Jose, CA (US);

Hugh W. Mcdevitt, San Jose, CA (US);

Carol Spanel, San Jose, CA (US);

Andrew D. Walls, San Jose, CA (US);

Inventors:

Michael J. Azevedo, San Jose, CA (US);

Hugh W. McDevitt, San Jose, CA (US);

Carol Spanel, San Jose, CA (US);

Andrew D. Walls, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method, apparatus and program storage device for providing self-quiesced logic for handling an error recovery instruction such as a reset or self-test instruction. For example, during a reset or self test procedure, the logic is isolated without adversely affecting the local processor. Self-quiesced logic processes an error recovery instruction by monitoring the processor interface for an idle condition and withholding access to the local processor. Once the local processor interface has been quiesced and the internal logic paths are idle, the logic will proceed with the reset or self-test.


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