The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 2009
Filed:
Feb. 28, 2007
John R. Kloeppner, Buhler, KS (US);
Dennis E. Gates, Wichita, KS (US);
Robert E. Stubbs, Longmont, CO (US);
Mohamad H. El-batal, Westminster, CO (US);
Russell J. Henry, Wichita, KS (US);
Charles E. Nichols, Wichita, KS (US);
John R. Kloeppner, Buhler, KS (US);
Dennis E. Gates, Wichita, KS (US);
Robert E. Stubbs, Longmont, CO (US);
Mohamad H. El-Batal, Westminster, CO (US);
Russell J. Henry, Wichita, KS (US);
Charles E. Nichols, Wichita, KS (US);
LSI Corporation, Milpitas, CA (US);
Abstract
Apparatus, systems and methods for clustering multiple PCI Express hierarchies to enable access of components in different hierarchies. Each PCI Express hierarchy includes a root device as well as a cluster port for coupling each hierarchy to each other hierarchy of a physical cluster through a PCI Express switched fabric. Memory addresses and transaction IDs are re-mapped by the cluster port of each hierarchy to partition the PCI Express space of the system of multiple hierarchies. A first portion of the partitioned space is reserved for access to local components within a hierarchy. A second portion of the space is used to access remote components of other hierarchies from within a different first hierarchy. The address and transaction ID values exchanged in such remote transactions are re-mapped and used by the cluster port of each hierarchy to route exchanges between hierarchies using standard PCIe root devices, endpoint devices, and switches.