The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2009

Filed:

Jun. 11, 2007
Applicants:

Nan-cheng Chen, Hsinchu, TW;

Chih-hui Kuo, Hsinchu, TW;

Jui-hsing Tseng, Hsinchu County, TW;

Ching-chih LI, Taipei County, TW;

Pei-san Chen, Taipei County, TW;

Inventors:

Nan-Cheng Chen, Hsinchu, TW;

Chih-Hui Kuo, Hsinchu, TW;

Jui-Hsing Tseng, Hsinchu County, TW;

Ching-Chih Li, Taipei County, TW;

Pei-San Chen, Taipei County, TW;

Assignee:

Mediatek Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Memory controllers and methods of optimizing pad sequences thereof are provided. At least two different preferred trace sequences on printed circuit boards for at least one memory device are first provided. One memory controller is then provided to have a core logic circuit, a plurality of input/output (I/O) devices, and a reorderer. The core logic has I/O terminals. Each I/O device on the single chip has a pad. The reorderer is coupled between the core logic circuit and the input/output devices, programmable to selectively connect the input/output devices to the input/output terminals. The reorderer is later programmed to select and connect a portion of the input/output devices to the input/output terminals such that one of the different preferred trace sequences is substantially supported.


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