The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 2009
Filed:
Dec. 19, 2007
Joseph O. Marsh, Poughkeepsie, NY (US);
Joseph Natonio, Wappingers Falls, NY (US);
James M. Wilson, Poughkeepsie, NY (US);
Joseph O. Marsh, Poughkeepsie, NY (US);
Joseph Natonio, Wappingers Falls, NY (US);
James M. Wilson, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of testing connectivity through a plurality of dual purpose current mode logic ('CML') latch circuits connected in a series is provided. Each of the CML latch circuits are operable to latch at least one output signal at a timing in accordance with at least one clock signal and having a mode control device for operating the CML latch circuit as a buffer amplifier when the at least one clock signal is inactive. The method comprises the steps of activating the mode control devices of each of the CML latches to operate each of the CML latches as a buffer; inputting a first signal to a first CML latch of the series; latching an output signal of a second CML latch of the series, the second CML latch being connected at a point in the series downstream from the first CML latch; and determining whether the output signal changes in accordance with a change in the first signal.