The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2009

Filed:

Mar. 07, 2007
Applicants:

Ji-hoon Cha, Seoul, KR;

Woo-gwam Shim, Yongin-si, KR;

Dong-gyun Han, Yongin-si, KR;

Chang-ki Hong, Seongnam-si, KR;

Seung-pil Chung, Seoul, KR;

Inventors:

Ji-hoon Cha, Seoul, KR;

Woo-gwam Shim, Yongin-si, KR;

Dong-gyun Han, Yongin-si, KR;

Chang-ki Hong, Seongnam-si, KR;

Seung-pil Chung, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a nonvolatile semiconductor memory device may include forming a pad oxide layer pattern and a mask pattern on a semiconductor substrate, forming a trench within the semiconductor substrate with the mask pattern functioning as an etching mask, sequentially forming a first device isolation layer and a second device isolation layer that may fill the trench, forming an opening by removing the mask pattern to expose an upper surface of the pad oxide layer pattern and a sidewall of the second device isolation layer, and forming a floating gate forming region having a width wider than the opening by simultaneously removing the pad oxide layer pattern and a sidewall portion of the second device isolation layer exposed by the opening.


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