Wiring structure and method of semiconductor integrated circuit

Abstract

To provide wiring structure and method capable of supplying a scan clock signal for each clock domain without requesting a user to add a test circuit. The wiring structure of a semiconductor integrated circuit according to an embodiment of the present invention includes: a fixed layer where a common line independent of a user circuit is formed; and a customized layer which is formed on the fixed layer and in which a line dependent on the user circuit is formed. The fixed layer is provided with a scan clock line supplying a scan clock signal for scan test to the selecting circuit, and a clock line supplying an output signal of the selecting circuit to a flip-flop of a scan path, and the customized layer is provided with a user clock line supplying a user clock signal to the selecting circuit.