The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2009
Filed:
Jan. 04, 2005
Tetsujiro Kondo, Tokyo, JP;
Kenji Takahashi, Kanagawa, JP;
Hiroshi Sato, Tokyo, JP;
Tsutomu Ichikawa, Kanagawa, JP;
Hiroki Tetsukawa, Kanagawa, JP;
Masaki Handa, Kanagawa, JP;
Tetsujiro Kondo, Tokyo, JP;
Kenji Takahashi, Kanagawa, JP;
Hiroshi Sato, Tokyo, JP;
Tsutomu Ichikawa, Kanagawa, JP;
Hiroki Tetsukawa, Kanagawa, JP;
Masaki Handa, Kanagawa, JP;
Sony Corporation, Tokyo, JP;
Abstract
A data storage unit is provided in which all data are stored into a memory including a plurality of memory banks and a plurality of desired data is read simultaneously, without any load to the hardware. It includes a memory controlling means including a data storage controller (), data read controllerand data move controller (), for judging, based on an access pattern representing a plurality of desired data to be read simultaneously when storing data sequentially into the memory with the data being divided among the plurality of memory banks of the memory, whether the data going to be stored are ones at locations corresponding to the access pattern, and storing all data at the locations corresponding to the access pattern into different memory banks by skipping a memory bank in which the data is to be stored, by incrementing its address, when the data to be read simultaneously are ones at the locations corresponding to the access pattern, and storing data at the locations corresponding to the access pattern into the memory bank having the bank address thereof incremented. The memory controlling means provides a control to read a plurality of desired data simultaneously from a memory ().