The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2009

Filed:

Oct. 25, 2005
Applicants:

Yuriy M. Greshishchev, Kanata, CA;

Graeme B. Boyd, North Vancouver, CA;

Larrie Carr, Anmore, CA;

Inventors:

Yuriy M. Greshishchev, Kanata, CA;

Graeme B. Boyd, North Vancouver, CA;

Larrie Carr, Anmore, CA;

Assignee:

PMC-Sierra, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 25/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and apparatus nullify an intrinsic jitter component in a digital clock recovery circuit induced by a time base frequency difference between an incoming data signal and a local synchronization clock for the digital clock recovery circuit. The techniques disclosed herein permit a recovered clock signal to be digitally filtered and applied to the digital clock recovery circuit clock synthesis unit (CSU) as a synchronization reference clock signal, which advantageously eliminates a time base frequency difference to reduce that jitter component and also reduces an intrinsic jitter component associated with jitter already present in the incoming data signal. In one embodiment, a state machine uses a filtered version of a recovered clock signal as a reference when the frequency of the filtered version of the recovered clock signal is relatively close to the frequency of the CSU reference clock signal.


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