The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2009
Filed:
Sep. 30, 2008
Sebastian Ehrenreich, Schoenau, DE;
Werner Juchmes, Boeblingen, DE;
Atnje Mueller, Boeblingen, DE;
Silke Salewski, Holzgerlingen, DE;
Sebastian Ehrenreich, Schoenau, DE;
Werner Juchmes, Boeblingen, DE;
Atnje Mueller, Boeblingen, DE;
Silke Salewski, Holzgerlingen, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for bypassing a memory array in a circuit having a global bit line, a test port configured to output a logic test, a memory portion connected to the global bit line via a word line, a header device being connected to the global bit line via a pre-charge signal, the header device being configured to recharge the global bit line. A gating signal is sent to a gating device connected to the header device. The gating device is switched to a test mode upon receipt of the gating signal. The bypass data signal is sent to an evaluating device connected to the gating device, the evaluating device being configured to output a logic test. The logic test is output through the test port upon receipt of bypass data signal.