Semiconductor memory and testing method of same

Abstract

Column switches are disposed for sense amplifiers respectively and are selectively turned on according to a column address to connect the sense amplifiers to a common data line. A sense amplifier control circuit activates a sense amplifier activation signal to operate the sense amplifiers. During a test mode, the sense amplifier control circuit changes time interval from activation of a word line to the activation of the sense amplifier activation signal, according to the column address. Then, a time interval after data is read to a bit line from a test target memory cell until the corresponding sense amplifier starts an amplifying operation is made constant irrespective of the position of the memory cell. Consequently, the same test condition can be set for the memory cells irrespective of the memory cells' positions. Correct evaluation of operation margins of the memory cells is possible irrespective of the positions of memory cells.