The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2009
Filed:
Jul. 20, 2006
Jeffrey B. Shealy, Huntersville, NC (US);
Matthew Poulton, Concord, NC (US);
Ramakrishna Vetury, Charlotte, NC (US);
Jeffrey B. Shealy, Huntersville, NC (US);
Matthew Poulton, Concord, NC (US);
Ramakrishna Vetury, Charlotte, NC (US);
RF Micro Devices, Inc., Greensboro, NC (US);
Abstract
The present invention is a hybrid integrated circuit comprising at least two semiconductor dies. A high performance semiconductor die includes high performance epitaxy layers grown on a donor substrate, which may form active devices such as transistors. A supporting semiconductor die includes epitaxy layers of a commercially available technology and grown on a native substrate to form passive devices such as resistors, capacitors, inductors, backside via holes, or active devices such as transistors The semiconductor dies are attached to a metallic mounting structure and may be electrically interconnected using traditional IC interconnect methods, such as wire bonding. The metallic mounting structure may function as a grounding base, which may be formed of electrically conductive metal such as copper. The high performance epitaxy layers may include GaN epitaxy layers, AlGaN epitaxy layers, SiC epitaxy layers, or a combination of the three.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile