The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2009

Filed:

Jul. 18, 2006
Applicants:

Paul Joseph Murtagh, Duluth, GA (US);

Prashant Shamarao, Alpharetta, GA (US);

Alejandro Flavio Gonzalez, Alpharetta, GA (US);

Inventors:

Paul Joseph Murtagh, Duluth, GA (US);

Prashant Shamarao, Alpharetta, GA (US);

Alejandro Flavio Gonzalez, Alpharetta, GA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A DRAM interface circuit includes a clock generation circuit configured to generate a plurality of internal clock signals and skew data in response to a plurality of data strobe signals (DQS) received at an interface of the integrated circuit device. A data capture circuit is also provided. The data capture circuit is configured to capture a plurality of data streams (DQ) associated with the plurality of data strobe signals in a manner that sufficiently reduces skew between the captured data streams so that all of the plurality of data streams may then be reliably captured in-sync with a common clock.


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