The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 2009
Filed:
Jul. 12, 2007
Applicants:
Chung-kuan Cheng, San Diego, CA (US);
Zhengyong Zhu, Sunnyvale, CA (US);
Inventors:
Chung-Kuan Cheng, San Diego, CA (US);
Zhengyong Zhu, Sunnyvale, CA (US);
Assignee:
The Regents of the University of California, Oakland, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
Techniques are described for performing analysis of circuits with nonlinear circuit components such as transistors based on a two-stage Newton-Raphson approach.
Cheng, Chung-Kuan. (2009). Efficient transistor-level circuit simulation (U.S. Patent No. 7555416). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7555416
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile