The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 2009
Filed:
Aug. 04, 2004
Walter C. Lin, Santa Clara, CA (US);
Jiande Jiang, San Jose, CA (US);
Walter C. Lin, Santa Clara, CA (US);
Jiande Jiang, San Jose, CA (US);
Trident Microsystems (Far East) Ltd., Taipei, TW;
Abstract
The present invention provides a system and method for adjusting clock phase in a digital display. The displaymay include a target analog-to-digital converterthat generates a first digital signal based on an analog input signal and a first clock signal (CLK). The systemincludes a first clock phase adjustment circuit, which provides CLKto the target analog-to-digital converter. A second analog-to-digital converterreceives at least a portion of the analog input signal and a second adjusted clock signal (CLK), and generates a second digital signal based on these inputs. A second clock phase adjustment circuitis communicatively coupled to the second analog-to-digital converter, and transmits CLKto the second analog-to-digital converter. A controllerreceives the second digital signal from the second analog-to-digital converterand uses the signal to determine a preferred phase of CLK. The controllerthen causes the first clock phase adjustment circuit to adjust the phase of CLKbased on the preferred phase.