The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 2009
Filed:
Sep. 19, 2007
Sergey V. Alenin, Tucson, AZ (US);
Junlin Zhou, Tucson, AZ (US);
Sergey V. Alenin, Tucson, AZ (US);
Junlin Zhou, Tucson, AZ (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
Circuitry for preventing damage to differentially coupled input JFETs in an integrated circuit amplifier includes first (J) and second (J) differentially coupled input JFETs. A first input signal (Vin+) is applied to a gate of the first input JFET (J), and second input signal (Vin−) is applied to a gate of the second input JFET. Needed amounts of drain current are supplied to the first and second input JFETs. A separator JFET (J) having a drain coupled to a source of the first input JFET and a source coupled to the source of the second input JFET is operated to control an amount of electrical isolation between the drain and source of the separator JFET so as to limit an amount of reverse bias voltage across a gate-source junction of one of the first and second input JFETs to a value less than a gate-source junction breakdown voltage of that the first and second input JFETs.