The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2009

Filed:

Mar. 29, 2007
Applicants:

Seong-goo Kang, Cheonan-si, KR;

Jun-ho Lee, Yongin-si, KR;

Ki-sang Kang, Yongin-si, KR;

Hyun-seop Shim, Incheon, KR;

Do-young Kam, Suwon-si, KR;

Jae-il Lee, Yongin-si, KR;

Ju-il Kang, Cheonan-si, KR;

Inventors:

Seong-goo Kang, Cheonan-si, KR;

Jun-ho Lee, Yongin-si, KR;

Ki-sang Kang, Yongin-si, KR;

Hyun-seop Shim, Incheon, KR;

Do-young Kam, Suwon-si, KR;

Jae-il Lee, Yongin-si, KR;

Ju-il Kang, Cheonan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device test handler for maintaining stable temperature in a test environment may include a loading unit that loads a plurality of semiconductor devices mounted on a test tray; a soak chamber configured to receive the test tray from the loading unit and to age the semiconductor devices at an aging temperature; and a test chamber configured to receive and test the aged semiconductor devices. The test chamber may include: a test board; a first chamber; a second chamber; one or more pipelines connected to the first and second chambers that allow a temperature-control medium to flow between the first and second chambers; a de-soak chamber that further ages the tested semiconductor devices so that the tested semiconductor devices substantially return to ambient temperature; and a sorting and unloading unit that sorts the tested semiconductor devices according to results of the test and that unloads the sorted semiconductor devices.


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