The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 2009
Filed:
Aug. 10, 2006
Sung-ho Jang, Gyeonggi-do, KR;
Sang-ho Song, Seoul, KR;
Sung-sam Lee, Gyeonggi-do, KR;
Min-sung Kang, Gyeonggi-do, KR;
Won-tae Park, Gyeonggi-do, KR;
Min-young Shim, Gyeonggi-do, KR;
Sung-Ho Jang, Gyeonggi-do, KR;
Sang-Ho Song, Seoul, KR;
Sung-Sam Lee, Gyeonggi-do, KR;
Min-Sung Kang, Gyeonggi-do, KR;
Won-Tae Park, Gyeonggi-do, KR;
Min-Young Shim, Gyeonggi-do, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.